STT-MTJ is viewed as a promising technology for next generation non-volatile memory, as its known potential features include fast switching, high switching cycle endurance, low power consumption, and extended unpowered archival storage.
In operation an STT-MTJ element is switchable between two mutually opposite, stable magnetization states—“parallel” (P) and “anti-parallel” (AP), by passing an electric “write” current through its layers. Provided the write current is above a given critical point (CPT) the STT-MTJ will switch into the P or AP induced by the direction of the write current. A conventional STT-MTJ memory cell stores one bit, with one of the P and AP states assigned to represent a first binary value, e.g., a “0”, and the other assigned to represent a second binary value, e.g., a “1.” The stored binary value can be read because STT-MTJ elements have a lower relative electrical resistance in the P state than the AP state.
Conventional STT-MTJ memory employs write circuitry designed and constructed to inject a write current having a magnitude high enough and duration long enough to ensure it switches the STT-MTJ element to the correct P/AP state—with a probability target of unity. Conventional design philosophy for STT-MTJ memory is therefore a “deterministic” writing confined to the design paradigm of conventional memories, such as SRAM, where the switching of memory elements is deterministic.
Conventional design philosophy of deterministic STT-MTJ writing, however, necessarily includes design rules that obviate, to the fullest extent possible, the fact that STT-MTJ elements do not have a precise, repeatable, threshold at which AP→P or P→AP switching occurs.
This reason is illustrated in the FIG. 1 simulation graph 100. The included simulation graph 102A shows an example probability of STT-MTJ element switching P/AP states as a function of pulse width t, using a write pulse 104 current level above CPT. FIG. 1 simulation graph 102B shows, in contrast, probability of an STT-MTJ element switching P/AP states as a function of pulse width t, but using a write pulse 106 current level that is lower than CPT. As illustrated, although still conditional on the pulse width, at the increased write current level the probability of switching increases much more sharply than that seen with the lower pulse current level.
Therefore, obtaining acceptable write performance with conventional deterministic programming, meaning a write error rate below a given maximum bit error rate (BER) without an excessive pulse width, generally necessitates a write current level substantially above CPT. This is further illustrated at the FIG. 2 graph 200 of pulse width 202 versus probability of switching 204, where simulation switching probability curve 206 corresponds to a write current above the critical level. Point 2050 shows an example pulse duration of required for near unity probability of switching. These pulse current levels and durations that are necessary in conventional deterministic programming consume extra power and take extra time in the effort to approach deterministic switching. Referring to FIG. 2, to give perspective the probability curve 220 corresponds to a current, well below CPT, on which point 2052 shows an example read point.
In addition, conventional STT-MTJ memory requires read/write access and control circuitry for each STT-MTJ resistive element. Conventional STT-MTJ memory therefore requires a complete STT-MTJ memory cell for each bit of storage. Further, in each of the memory cells the STT-MTJ element footprint generally occupies a minor portion of the cell area. Increasing the size of an n row by m column (hereinafter “n×m”) STT-MTJ array to larger values of m and n does nothing to remove this inefficiency.